1. Field of the Invention
The present invention relates to a dicing sheet, a manufacturing method thereof, and a manufacturing method of a semiconductor apparatus.
Priority is claimed on Japanese Patent Application No. 2004-204499 filed Jul. 12, 2004, the content of which is incorporated herein by reference.
2. Description of Related Art
A manufacturing method of a semiconductor chip is performed by the following method, that is, a predetermined pattern of the integrated circuit is formed on a semiconductor wafer, and the predetermined pattern of the integrated circuit thereof is cut away, and is divided into parts. The cutting of the wafer is called dicing. In the dicing process of the semiconductor wafer, using a holding member in which an adhesive film (dicing sheet) having an adhesive agent at one side thereof is applied at one surface side of a ring shape of frame of which the size is larger than the size of the semiconductor wafer, a rotation blade is penetrated with regard to the semiconductor wafer in the state in which the semiconductor wafer is attached to the dicing sheet, while each semiconductor wafer is moved along the cutting line (dicing line) which distinguishes each semiconductor wafer, and thereby each semiconductor wafer is divided (for example, Patent Document 1: Japanese Unexamined Patent Application, First Publication No. S61-180442, Patent Document 2: Japanese Unexamined Patent Application, First Publication No. S63-29948).
By the way, at present, because it is necessary for the electronic apparatus having portability such as the portable phone, the notebook type of personal computer, PDA (Personal data assistance), or the like, or the apparatus such as the sensor, the microdevice, the head of a printer, or the like to be miniaturized and the weight reduced, miniaturization of various electric parts such as the semiconductor chip, or the like which is provided at the inside of the above apparatus is attempted. Moreover, the mounting space of the electric parts is extremely limited. Thereby, in order to perform the further high integration, both semiconductor chips which have the same function as each other, or both semiconductor chips which have different functions from each other are laminated, the electrical connection between each semiconductor chip is carried out, and thereby three-dimensional mounting technology which plans the high density mounting of the semiconductor chips is also considered. Furthermore, in the semiconductor chip using such three-dimensional mounting technology, electrodes are formed at both the front surface and the back surface thereof, while the through hole which penetrates the semiconductor chip is provided, and the electrode structure is provided in which both electrodes of the front surface and the back surface is electrically connected via the electric member (penetration electrode) which is filled in the through hole.
By laminating the semiconductor chips which are provided with such electrode structure, the wiring connection between the laminated semiconductor chips can be easily performed.
However, when the semiconductor chip which is provided with the above-mentioned electrode structure is made, it becomes clear that the defect in the dicing process easily occurs. That is, when the semiconductor wafer in which the penetration electrode is formed is adhered to the dicing sheet, because the penetration electrode is projected from the adhesion surface of the semiconductor wafer, it turns out that the close adhesion between the dicing sheet and the semiconductor wafer is inhibited, and the chip peeling or the chip floating at the time of cutting occurs. Even if the chip peeling, or the like does not occur, because the close adhesion between the dicing sheet and the semiconductor wafer is weak, the dust (cutting dust) which is generated by the dicing is mixed in the gap between the sheet and the semiconductor wafer, and thereby it is possible for the semiconductor wafer to be contaminated. Furthermore, because the holding of the semiconductor wafer is not sufficient, cracking may arise in the cutting surface of the semiconductor wafer.